Among known flash memory cells, the dual-poly floating-gate EPROM tunnel oxide (ETOX) memory cell is one of the most popular. Its floating poly gate serves as a charge storage element. However, a conventional ETOX type memory cell faces significant engineering challenges. Compared to ETOX memory cells, silicon-oxide-nitride-oxide-silicon (SONOS) flash memory cells have a thinner gate-stack, and therefore are better candidates for scaling and process integration.
Currently, SONOS flash memory cells are based on the planar MOSFET transistor with a silicon-oxide-nitride-oxide-silicon gate structure. FIG. 1A illustrates a planar SONOS flash memory cell. A nitride layer (floating gate) 4 is used for trapping and storing charges representing digital data “1” or “0.” Charges can also be trapped locally in the oxide-nitride-oxide (ONO) structure, which comprises an oxide 2, nitride 4, and oxide 6, near source 8 or drain 10 for 2-bits-per-cell storage. The charge-trapping layer (nitride) 4 in SONOS flash memory cells can also be advantageously replaced by another high-k dielectric for better charge retention, less over-erasing, etc.
However, the development of the SONOS flash memory cell faces challenges. Planar SONOS flash memory cells have a relatively thicker ONO structure (including bottom tunnel oxide, charge trapping SiN, and top oxide) than thin-gate CMOS transistors, and thus are more difficult to scale than thin-gate MOS transistors. This posts severe limitations on SONOS flash memory cells due to short channel effects.
Nitride sidewall (or spacer) trapping has been proposed for 2-bit storage in ETOX or SONOS flash memory. Additionally, gate-induced-drain-leakage (GIDL) was recently proposed for read operations due to its modulation by trapped charges in the floating gate (for ETOX memory cells) or in the nitride layer. However, in conventional sidewall trapping memories, due to the conventional channel-hot-electron (CHE) programming, charge injection toward sidewall spacers is sensitive to the position of the source/drain junction boundary. As a result, portions of the channel need to be directly underneath the spacers in order to achieve acceptable hot carrier injection. This will increase the channel length and the capacitance between the gate and the source/drain regions, making the memory cells hard to scale.
Most recently, SONOS type flash memory cells based on non-planar FinFETs have been proposed for taking advantage of FinFET's superior scalability. As is known, non-planar CMOS transistors (such as FinFETs or also known as tri-gate MOSFETs) are capable of much better gate control, leading to suppressed short channel effects at 45 nm and below. FIG. 1B illustrates a conventional SONOS type FinFET flash memory cell. It is evolved from the planar version of a SONOS flash memory cell, however, with better gate control and better scalability. The memory cell includes a fin 12, a gate 20, and a charge storage region 16 between two oxides 14 and 18.
The SONOS FinFET memory cell shown in FIG. 1B has better scaling capability. Unfortunately, it loses the capability for storing 2 bits per cell since the smaller gate length results in an inability to distinguish between local charges stored near the source and drain sides, respectively. For example, stored charges typically span around 40 nm. With charges stored on both ends, a gate length smaller than 100 nm will be marginal in its ability to maintain 2-bit storage capability. Additionally, the injection efficiency of charge will decrease significantly for very short channels. This is due to the carriers transporting along the channel in a more ballistic manner. The impact ionization mostly occurs after carriers entering the source/drain extension region reach heavily doped source/drain regions. Generated charges are therefore far away from the charge storage region.
Thus, there is the need for a method of fabricating a new memory cell structure, which is not only scalable in channel length, but also capable of storing 2-bits per cell with a more efficient hot carrier injection mechanism.